On x86-64 (a TSO architecture), a release store followed by an acquire load on a different atomic variable is used in a Dekker-style mutual-exclusion idiom. Why can this still break even though the architecture itself never reorders stores past later stores?

std::atomic<int> x{0}, y{0}; // Thread 1 // Thread 2 x.store(1, std::memory_order_release); y.store(1, std::memory_order_release); int r1 = y.load(std::memory_order_acquire); int r2 = x.load(std::memory_order_acquire); // Can r1 == 0 && r2 == 0 ?

On x86-64 (a TSO architecture), a release store followed by an acquire load on a *different* atomic variable is used in a Dekker-style mutual-exclusion idiom. Why can this still break even though the architecture itself never reorders stores past later stores?

On x86-64 (a TSO architecture), a release store followed by an acquire load on a different atomic variable is used in a Dekker-style mutual-exclusion idiom. Why can this still break even though the architecture itself never reorders stores past later stores?